Research: Evaluation of Sub-Threshold CMOS Techniques for Energy-Efficient IoT Endpoint...

Research question: How do sub-threshold CMOS circuit techniques impact the power consumption and reliability of ultra-low-power IoT endpoint devices under varying operating conditions?

Background & Motivation: The proliferation of Internet-of-Things (IoT) devices has driven demand for ultra-low-power electronics, particularly at endpoints relying on battery or energy-harvesting sources. Traditional CMOS designs have reached limits in power efficiency, prompting interest in sub-threshold operation, where transistors operate below the threshold voltage, drastically reducing power consumption.

Research Gap: While sub-threshold CMOS techniques offer theoretical benefits, practical challenges remain in maintaining circuit reliability and performance, especially under process variations and environmental fluctuations. There is limited empirical analysis of how these techniques perform across different IoT endpoint workloads and scenarios.

Approach & Expected Contribution: This study will systematically review state-of-the-art sub-threshold CMOS literature, formulate hypotheses regarding energy savings and reliability trade-offs, and design experiments using circuit simulation and prototype fabrication. The project aims to quantify power and reliability metrics, identify optimal design parameters, and provide actionable insights for future IoT endpoint designs.

Significance: Results will inform designers on the feasibility and limitations of sub-threshold CMOS, supporting the development of sustainable, battery-free IoT systems crucial for smart environments and pervasive sensing.