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Research: Design and Evaluation of an Energy-Efficient CNN Inference Accelerator for Ed...

Field: Electronics & Communication Type: Research project Bloom: Create / Evaluate Level: Final-year / PG capstone Inspired by: MIT / Stanford / Oxford research agendas

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About this project
Research: Design and Evaluation of an Energy-Efficient CNN Inference Accelerator for Edge AI on FPGA Platforms

Research question: How can a custom FPGA-based accelerator architecture be designed to achieve energy-efficient CNN inference for edge-AI applications compared to existing state-of-the-art implementations?

Background & Motivation: Convolutional Neural Networks (CNNs) have become foundational in computer vision and edge-AI applications, but their computational complexity poses challenges for real-time, low-power inference on resource-constrained edge devices. FPGAs offer a promising platform for custom hardware acceleration due to their reconfigurability and potential for energy optimization.

Research Gap: While prior work has demonstrated FPGA-based CNN accelerators, there is limited systematic evaluation of architectural and algorithmic co-design strategies to maximize energy efficiency specifically for modern edge-AI workloads. Furthermore, quantitative comparisons of energy, performance, and accuracy trade-offs across design choices are sparse in open literature.

Approach & Expected Contribution: This project will investigate architectural optimizations (e.g., quantization, data reuse, memory hierarchies) for CNN inference on FPGA, proposing a novel accelerator design. The methodology involves literature review, architectural modeling, implementation using high-level synthesis (HLS), and benchmarking on standard CNN models (e.g., CIFAR-10, ImageNet subsets). Power and performance metrics will be collected using on-board instrumentation, and results compared to reference implementations. The expected contribution is a quantitative, reproducible evaluation framework and a prototype achieving improved energy efficiency for targeted edge scenarios.

Why it Matters: Improving the energy efficiency of AI inference at the edge is critical for pervasive autonomous systems, IoT, and mobile healthcare. This research will inform future edge-AI hardware design by identifying effective architectural strategies, with potential impact on battery life, environmental footprint, and deployment of intelligent systems in power-sensitive domains.

Milestones
1. Literature Review & Problem Definition
15 marks 18d
Conduct an in-depth review of current FPGA-based CNN accelerators, define the research problem and identify the performance-energy gaps.
2. Research Proposal & Hypotheses
10 marks 14d
Develop the research proposal detailing objectives, review feedback, and formulate testable hypotheses for the accelerator design.
3. Methodology & Experimental Design
20 marks 18d
Design the accelerator architecture, select benchmark models and datasets, and outline experimental protocols for evaluation.
4. Data Collection / Experimentation
20 marks 20d
Implement the proposed accelerator on FPGA, run inference workloads, and collect power and performance data.
5. Analysis & Results
15 marks 14d
Analyze collected data, perform statistical comparisons, and interpret results relative to research hypotheses and literature baselines.
6. Thesis Write-up & Defense
20 marks 18d
Compile the final thesis, prepare presentation materials, and defend findings before examiners.
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Upcoming sessions
SessionWindowEnrolled
Research: Design and Evaluation of an Energy-Efficient CN... 11 Jun 2026 to 10 Jun 2028 0
Skills you'll learn
ResearchElectronics & CommunicationComprehensive literature review in edge-AI hardware and FPGA-based acceleratorsFormulation of research hypotheses and experimental objectivesMethodology and experimental design for hardware-software co-evaluationImplementation and verification of hardware accelerators using HLS toolsQuantitative data collection of energy and performance metricsStatistical analysis and result interpretationAcademic writing and oral defense of research findingsDomain knowledge in digital designmachine learningand embedded systems
Tools used
Xilinx Vivado Design SuiteVitis HLS (High-Level Synthesis)PYNQ or Zynq FPGA development boardsPython and C/C++ for accelerator integration and benchmarkingPower measurement tools (e.g.Xilinx Power Estimatoronboard power monitors)Standard CNN models and datasets (e.g.CIFAR-10ImageNet subset)MATLAB or Python for statistical analysis
Prerequisites
Digital Logic DesignEmbedded SystemsVLSI Design PrinciplesIntroduction to Machine Learning or Deep LearningComputer Architecture
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