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FPGA-Based Real-Time Image Processing Accelerator for Edge IoT Applications

Branch: Electronics Engineering Type: Industry-applied final-year Major Project Standard: Mumbai University Rev-2019 'C' Scheme (Major Project I + II) Group: up to 4 students Assessment: 6 review-based milestones (100 marks)

Real-world project · AICTE-aligned · AI-graded · Audit-ready certificate

6
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Enrolled students
15
Core skills
About this project

Objective: To design, implement, and validate a low-latency FPGA accelerator for real-time image processing on resource-constrained edge devices.

Real-world problem: Many industrial, medical, and smart city applications in India require real-time image processing at the edge—for example, in traffic surveillance, smart agriculture, and biomedical monitoring—where cloud connectivity is limited or latency is critical. Traditional CPUs or MCUs on edge devices struggle with the computational demands of image processing, resulting in slow response times and high power consumption.

Proposed solution: This project aims to develop a field-programmable gate array (FPGA)-based hardware accelerator tailored for real-time image processing tasks such as object detection, edge detection, and filtering. The system will be designed as a plug-in module for existing edge IoT platforms, leveraging parallel hardware logic to dramatically improve processing speed and energy efficiency over traditional software approaches.

Key features and deliverables: The project will deliver a working prototype comprising a low-cost FPGA development board (such as Xilinx Artix-7), an interfaced camera module (e.g., OV7670), and a software stack for integration with edge devices (such as Raspberry Pi or ARM-based SoCs). Demonstrations will include live video feed processing with measurable improvements in latency and power usage, along with detailed documentation, cost analysis, and industry-aligned paper/report.

Industry impact: The accelerator prototype can be adapted for Indian industry use cases in surveillance, agriculture, and healthcare, enabling affordable, scalable, and energy-efficient edge vision solutions. The design is modular, standards-compliant (VHDL/Verilog), and suitable for commercial prototyping or further academic research.

Milestones
1. Synopsis & Problem Definition (Stage-I Review-1)
8 marks 24d
Submit a clear synopsis defining the problem, objectives, and initial feasibility, reviewed by the project guide.
2. Literature / Market Survey & Requirement Analysis (Stage-I Review-2)
12 marks 27d
Present a comprehensive survey of existing FPGA accelerators and market solutions, with detailed requirement analysis and application mapping, reviewed in a departmental seminar.
3. System Design, Methodology & Cost Analysis (Stage-I close)
20 marks 36d
Deliver detailed system architecture, algorithm-to-hardware mapping, component selection, and cost analysis for faculty approval.
4. Implementation / Fabrication of Working Model (Stage-II Review-1)
25 marks 42d
Develop and assemble the FPGA image processing module, including hardware interfacing and basic functionality demonstration, reviewed via lab inspection.
5. Testing, Results & Validation (Stage-II Review-2)
20 marks 38d
Conduct rigorous testing with real-world image datasets, measure speed-up and power savings, and validate against benchmarks; reviewed through demonstration and data submission.
6. Report, Paper & Demonstration / Oral Defense (Stage-II final Oral & Practical)
15 marks 28d
Submit a comprehensive technical report, IEEE-format paper, and conduct a live demonstration/oral defense before the examiner panel.
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Upcoming sessions
SessionWindowEnrolled
FPGA-Based Real-Time Image Processing Accelerator for Edg... 11 Jun 2026 to 10 Jun 2028 0
Skills you'll learn
CapstoneFinal-year projectMajor projectElectronics EngineeringFPGA hardware design and HDL (VHDL/Verilog) programmingEmbedded system integration (camera modulesedge platforms)Digital image processing algorithm implementationSystem-level design and cost analysisPCB design and hardware interfacingTestingvalidationand benchmarkingTechnical documentation and paper writingTeamwork and project management
Tools used
Xilinx Vivado Design SuiteXilinx Artix-7 FPGA boardOV7670 camera moduleHDL (VHDL/Verilog)Raspberry Pi or BeagleBone Black (for edge integration)MATLAB or Python (for algorithm development and benchmarking)IS/IEC 61508 (Functional Safety Standard) for reference
Prerequisites
Digital System DesignEmbedded SystemsMicroprocessors and MicrocontrollersSignals and SystemsBasic Image Processing
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